Key factors in STTRAM development include reducing STT writing current and voltage (energy) while maintaining adequate thermal stability. The memory cell consists of a semiconductor isolation device and a magnetic tunnel junction with two ferromagnetic layers separated by a MgO-based tunneling barrier layer in which thickness is controlled to approximately 1 nm. The spin transfer torque memory (STTRAM) is an advanced version of the magnetic RAM with a different write mechanism. A difficult challenge of the suspended-beam NEMM is scalabily: according to a recent study, it might be difficult to achieve low-voltage (~1 V) operation for the beam length less than 50 nm.
Several different modifications of suspended-beam NEMMs are currently being explored using different materials including carbon nanotubes, Si, Ge, and TiN. In this concept, mechanical digital signals are represented by displacements of solid nanoelements, which result in closing or opening an electrical circuit. The nanoelectromechanical memory (NEMM) is based on a bi-stable nano-electromechanical switch. Another important challenge is the rather short retention time, approximately 30 days, for the FeFET. In addition, the major challenge is the long-term reliability related to the ferroelectric-semiconductor interface. Scaling is projected to end approximately with the 22 nm generation, because the insulation layer becomes too thin and the properties of the ferroelectric with respect to thickness dependence of the coercive field will not allow further reduction.
For this reason it is very difficult to fabricate a FeFET with excellent electrical properties.
At the channel interface, a high quality insulator is required to guarantee a low interface state density. The ferroelectric polarization directly affects charges in the channel and leads to a defined shift of the output characteristics of the FET. The ferroelectric field effect transistor (FeFET) is a one transistor (1T) memory device where a ferroelectric capacitor is integrated into the gate stack of a FET. Some promising memory technologies have been developed for the next-generation flash memory to go beyond the current floating-gate flash memory technology. Additionally, a limited margin poses a great challenge on the reliability of the floating-gate memory devices, as the number of electrons stored in floating-gate significantly decreases with continual down-scaling of the cell size. Moreover, as the spacing between adjacent devices is down-scaled, this parasitic capacitance plays an increasingly dominant role in the device performance due to data stored in the adjacent cells can interfere with each other by capacitive coupling. In addition, maintaining a high gate coupling ratio is still one main bottle-neck for down-scaling the floating-gate devices. A relatively thick tunneling oxide and inter poly dielectric layer have to be used in the floating-gate memory to maintain acceptable reliability, limiting further down-scaling of the cell size in the vertical direction. As Flash memory device scales down beyond the 32 nm technology node, approaches face significant challenges. However, some intrinsic limitations make this type of memory rapidly approach the scaling limit. The ever-increasing fabrication density of Flash memory has been mainly driven by area scaling. Floating-gate flash memory has been successfully developed in the last few decades with continues down-scaling the dimensions of the cell to obtain high data-storage density, high program/erase speeds, low operating voltage and low power consumption. A non-volatile memory device is one that can retain stored information in the absence of power and flash memory is a type of non-volatile memory.
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